A number of electronic devices include one or more computing devices such as one or more central, processing units (CPU), one or more graphics processing units (GPU), one or more digital signal processors (DSP), and/or the like. The computing device, herein after simply referred to as a processor, executes computing device readable instructions (e.g., computer programs) and operates on data stored in one or more computing device readable media, herein after simply referred to as memory. To access instructions and data stored in memory, the processor may include one or more memory controllers and one or more memory interfaces. For example, a processor may include a memory controller and four memory interfaces for accessing frame buffer memory, as illustrated in FIG. 1. It is appreciated that the memory interface may be separate from or integral to the memory controller. However, for ease of understanding embodiments of the present technology, the conventional art and embodiments of the present technology will be described with regard to separate memory controllers and memory interfaces. The memory controller generally converts addresses in one memory space to addresses in another memory space. For example, the memory controller may convert logical addresses to physical addresses. The memory interface generally converts addresses in a given memory space to electrical signals to drive address, data and control lines, and receives electrical signals on the address data and control lines, for reading and writing data and/or computer readable instructions to or from the memory.
The processor also includes a number of other functional blocks not shown. For example, the processor may include a plurality of processor cores, one or more communication interfaces, and the like. Processors are well known in the art and therefore those aspects of the processor that are not germane to an understanding of the present technology will not be discussed further.
The performance of the processor is determined by a number of factors, including the amount of memory and the speed at which the memory can be accessed. One common method of improving performance of the processor is to attach the memory to the processor so that a plurality of accesses to memory can be performed substantially together. In one technique, the processor may include a plurality of memory interfaces, each coupled to one or more memory partitions. If each partition is 64 bits wide and there are four partitions, then a memory access to 512 bits can be accessed in two cycles by accessing a first 64 bits in each of the four partitions together and then accessing the next 64 bits in each of the four partitions together. Similarly, a memory access to 636 bits can be performed in three access cycles.
The processor is typically fabricated as an integrated circuit on a monolithic semiconductor substrate (IC chip). However, in other embodiments, the processor may be implemented by a plurality of separate integrated circuits. Typically, the memory is also fabricated as an integrated circuit on a monolithic semiconductor substrate. Usually, each memory partition supported by a processor includes one or more memory integrated circuit chips. For example, each partition of the memory may be implemented by a 256 MB integrated circuit chip.
The integrated circuit of a processor typically includes millions or more semiconductor devices, such as transistors, and interconnects there between. A plurality of processors are fabricated in an array on a wafer. For example, tens, hundreds or thousands of copies of the same processor may be fabricated on a wafer. One or more of the processors on the wafer will include one or more fabrication defects. To increase the fabrication yield from a wafer, a processor that includes a plurality of a given functional block may be configurable to disable one or more of the given functional blocks that includes a manufacturing defect. The device including the one or more of the given functional blocks that have been disabled can then be sold as a lower performance version of the processor. For example, one or more processor chips may include a defect in a particular memory interface, as illustrated in FIG. 2. The memory interface functional block that includes a manufacturing defect may be disabled and sold as a processor supporting 768 MB of frame buffer memory. In comparison, the computing device in FIG. 1, in which all four memory interface are enabled, are sold as processors supporting 1 GB of frame buffer memory.
In practice, manufactures have found it difficult to sell the lower performance versions of the processor. For example, a manufacturer of graphic processors may readily sell the GPUs supporting 1 GB of frame buffer memory, but find it difficult to sell the GPUs that support 768 MB of frame buffer memory even if the reduction does not appreciably affect the performance of the GPU. Accordingly, there is a continuing need for improved memory subsystems in computing devices such as central processing units, graphics processing, units, digital signal processing units, microcontrollers, and the like.
In other cases, a processor may not include manufacturing defects. However, one or more operational functional blocks of the processor may still be selectively disabled for one or more reasons. In such cases, there is a similar continuing need for improved memory subsystems in computing devices such as central processing units, graphics processing, units, digital signal processing units, microcontrollers, and the like.